1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a contact structure of a semiconductor device and a method of forming the same.
2. Description of the Related Art
In a semiconductor memory device, a cell selection signal is applied to a word line and a data signal is applied to a bit line, so that the data signal is applied to the selected cell. The bit line is in contact with the word line in the periphery region of the memory device. The word line and the bit line are formed to materials having good conductivity, for preventing signal delay. For example, they are generally formed to a tungsten polycide structure in which a tungsten silicide layer is formed on a doped polysilicon layer.
FIG. 1 shows a conventional contact structure between a word line and a bit line in the periphery region of a memory device.
Referring to FIG. 1, a word line 12 in which a first tungsten silicide (WSix) layer 12a is formed on a first doped polysilicon layer (doped ploy-Si) 12a is formed on a semiconductor substrate 10. An intermediate insulating layer 14 is then formed on the overall substrate and etched to expose the portion of the surface of the first tungsten silicide layer 12b of the word line 12, thereby forming a contact hole 16. Thereafter, a bit line 18 in which a second tungsten silicide layer 18b is formed on a second doped polysilicon 18a is formed on the surface of the contact hole 16 and on the intermediate insulating layer 14, to be contact with the word line 12 through the contact hole 16.
However, there are following problems in the contact structure of the word line 12 and the bit line 18 above described.
Firstly, owing to heterojunction of the second doped polysilicon layer 18a and the first tungsten silicide layer 12b at the contact portion, barrier height of about 0.65 eV. due to the difference of work functions xcfx86poly and xcfx86wsix between the two layers 18a and 12b exist, as shown in FIG. 2. Tunneling current therefore decreases when electrons are therefore migrate, thereby increasing contact resistance between the word line and the bit line.
Secondly, when performing etching for forming the contact, owing to sputtering yield difference and reaction difference of W and Si for plasma gas such as CxFy, CF4+O2, CHxFy and CHxBry is used as etching gas, the exposed surface of the first tungsten silicide layer 12b is rouged, so that contact resistance between the word line 12 and the bit line 18 further increases and contact interface therebetween is unstablized.
Thirdly, the plasma gas reacts with W and/or Si of the first tungsten silicide layer 12b, so that insulating compounds 100 having negative xcex94H as shown in TABLE 1 are created on the exposed surface of the first tungsten silicide layer 12b, and acts as factor increasing the contact resistance. As a result, signal delay time increases.
It is therefore one object of the present invention to provide a semiconductor device which can reduce contact resistance by decreasing the difference of the work functions in contact, for solving the problems in the conventional art.
Furthermore, it is another object of the present invention to provide a method of manufacturing a semiconductor device which can reduce contact resistance.
To accomplish one object of the present invention, a semiconductor device according to the present invention includes a lower conductor pattern and an upper conductor pattern. The lower conductor pattern is in contact with the upper conductor pattern. The lower conductor pattern includes a first doped polysilicon layer, a first tungsten silicide layer and a cap layer formed sequentially. Here, the cap layer is formed to a doped polysilicon layer containing a small amount of tungsten and having stoichiometrical equivalent ratio x of Si higher than the first tungsten silicide layer. The upper conductor pattern includes a second doped polysilicon layer and a second tungsten layer formed sequentially. The contact of the lower conductor pattern and the upper conductor pattern is substantially formed between the cap layer and the second doped polysilicon layer.
Preferably, stoichiometrical equivalent ratio x of Si for the first tungsten silicide layer is 2.3 to 2.5 and stoichiometrical equivalent ratio x of Si for the cap layer is 2.6 to 2.9.
Furthermore, to accomplish another object of the present invention, according to the present invention, firstly, a first doped polysilicon layer and a first tungsten silicide layer on a semiconductor substrate are formed, sequentially. A cap layer is then formed on the first tungsten silicide layer by in-situ after forming the first tungsten silicide layer. Here, the cap layer is formed to an undoped polysilicon layer containing a small amount of tungsten and having stoichiometrical equivalent ratio x of Si higher than the first tungsten silicide layer. Next, the cap layer, the first tungsten silicide layer and the first doped polysilicon layer are patterned to form a lower conductor pattern. An intermediate insulating layer is formed on the overall substrate and etched to expose a portion of the surface to the cap layer, thereby forming a contact hole. Thereafter, a second doped polysilicon layer and a second tungsten silicide layer are formed on the surface of the contact hole and on the intermediate insulating layer, sequentially and patterned to form an upper conductor pattern being in contact with the lower conductor pattern. Next, the substrate in which the upper conductor pattern is formed is annealed, to outdiffuse impurities of the second doped polysilicon layer into the cap layer, thereby doping the cap layer.
In this embodiment, the first tungsten silicide layer is formed by CVD using SiH2Cl2 (or SiH4) gas and WF6 gas as reactive gases at the temperature of 550 to 600xc2x0 C. Preferably, the ratio of SiH2Cl2 (or SiH4):WF6 is 8:1.5 to 10:2 and stoichiometrical equivalent ratio x for Si of the first tungsten silicide layer is 2.3 to 2.5.
Furthermore, the cap layer is formed by depositing a undoped polysilicon layer by in-situ after forming the first tungsten silicide layer using SiH2Cl2 (or SiH4) gas and WF6. Preferably, the ratio of SiH2Cl2 (or SiH4) WF6 to 9:0.8 to 11:1.2 and the stoichiometrical equivalent ratio x for Si of the cap layer is 2.6 to 2.9.
Moreover, the annealing is preformed at the temperature of 600 to 900xc2x0 C.
Additional object, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.